Implementation Of Risc Architecture In Simulink And FPGA

Mohd Rashidi, Md Puzi (2014) Implementation Of Risc Architecture In Simulink And FPGA. Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

This project is about the implementation of RISC processor architecture in Simulink and FPGA (Field Programmable Gate Array). RISC processor has been used in many computer-based applications nowadays comparing to CISC. This project aims to design RISC processor architecture in Simulink environment where it used a model-based design. The RISC architecture block diagram and designed in the Simulink, and then the architecture can be developed by gathering the entire required source for the MATLAB function be create the architecture. Most of the block used is the MATLAB function block source code. In the source code, the input and output for the entire module will be defined. To produce a working architecture, all the parameters for the RISC processor architecture can be set in the given parameter setting. Therefore, the error on the architecture can be minimized. By integrating the entire module, the architecture test program to test the functionality of the architecture. The test program used is the bubble sorting, where there will be an array of data to be sorted. The output can be display in the scope provided in the architecture. The HDL code can be generated using the HDL Coder provided in the simulink setting. Using the HDL Coder, the Verilog code can be provided for verification in the FPGA. This project focuses on 8-bit RISC processor and implemented using MATLAB 2013a/Simulink. As for the testing purpose, it will be implemented in Virtex 6 FPGA board.

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