Analysis Of 20NM SOI NMOS Device With Different Gate Spacer Dielectric

Goh, Siew Yun (2016) Analysis Of 20NM SOI NMOS Device With Different Gate Spacer Dielectric. Project Report. UTeM, Melaka, Malaysia. (Submitted)

Text (24 Pages) Analysis Of 20NM SOI NMOS Device With Different Gate Spacer Dielectric.pdf - Submitted Version Download (471kB)

Abstract

As scaling down MOSFET devices degrade device performance in term of leakage current and short channel effects. To overcome the problem a Silicon-on-Insulator (SOI) NMOS device has been introduced. Several investigations will be done to reduce the SCE in 20nm SOI NMOS device. This project execution is based on simulation and program development of the device. Simulation of this device fabrication is being performed by using ATHENA module while the simulation of electrical characteristics is being implemented by using ATLAS module from Semiconductor TCAD tools. Semiconductor TCAD tools are computer programs which allows for the creation, fabrication, and simulation of semiconductor devices. This work is also facilitating for the improvement of performance of 20nm SOI MOSFET using high-k gate spacer dielectric. Throughout this project, it has been proved that High-k spacer provides higher transconductance than conventional SiO2 spacer. It also provides higher voltage gain, so SOI MOSFET devices with high-k spacer can be use for amplification purpose. Also ION/IOFF is higher in case of high-k spacer. High-k spacer improve short channel effects by improving subthreshold slope than conventional SiO2 spacer. So, high-k gate spacer is better option for coming SOI MOSFET devices.

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