Application Of Taguchi Method In The Optimization Of The SOI MOSFET

Siti Rafiah, Ab Rashid (2015) Application Of Taguchi Method In The Optimization Of The SOI MOSFET. Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

This project is about the optimization of Silicon-On-Insulator (SOI) MOSFET device by applying Taguchi Method. Silicon-On-Insulator (SOI) wafers are bound to play a key role in next generations Complementary Metal Oxide Semiconductor (CMOS) nanometre technology. This method was used to analyse the experimental data in order to get the optimum results. In this paper, there are four factors were varied for 3 levels to perform 9 experiments which are Pocket-Halo Implant Dose, Pocket-Halo Implant Energy, Source/Drain Implant Dose and also Source/Drain Implant Energy. The traditional SOI structure consists of a silicon dioxide layer sandwiched between a top thin silicon layer in which devices are built and the silicon substrate. Meanwhile, SILVACO TCAD tools will be used to design SOI Metal Oxide Semiconductor Field Effect Transistor (MOSFET). The aim of this project is to design an 10nm SOI MOSFET device by using SILVACO TCAD tool, to analyse the electrical characterization of SOI MOSFET by using ATLAS SILVACO TCAD tool and to optimise the performance of SOI MOSFET device by applying Taguchi Method. One of the way to optimize the performance of the SOI MOSFET is to alter the SOI layer thickness and the electrical characteristic degraded when the effective gate length of SOI MOSFET was reduced. The best thickness is 10nm thickness layer of SOI MOSFET.

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