Current ratio analysis on design and modelling A 22 nm bilayer Graphene and high-K/metal gate (TiO2/ WSix) NMOS device

Kamalrul Ariffin, Nur Athirah Syuhada (2020) Current ratio analysis on design and modelling A 22 nm bilayer Graphene and high-K/metal gate (TiO2/ WSix) NMOS device. Project Report. Universiti Teknikal Malaysia Melaka, Melaka, Malaysia. (Submitted)

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Abstract

A 22nm of a bilayer Graphene NMOS transistor was designed and modeling based on virtual fabrication using Silvaco Software besides optimized current ratio using Taguchi L9 orthogonal array method. In this project, the materials used are high permittivity material (high-K) which is Titanium Dioxide (TiO2) and metal gate which is Tungsten Silicide (WSix). There are four Control Factor (CF) and two Noise Factor (NF) which have been considered to get a good result for threshold voltage and leakage current. As the result of VTH optimization, Halo Tilt angle is the adjustment factor while Compensation Implant was selected as dominant factor. Meanwhile, the dominant factor for ILEAK optimization is Compensation Implant. From L9 Taguchi, the VTH value of 0.289433V and ILEAK value of 5.61104 nA/μm were achieved which closer to the ITRS 2012 prediction which is 0.289 V ± 12.7% for threshold voltage and lower than 100nA/μm for leakage current. Finally, the value of current ratio obtained is 4.4822x104.

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