Current ratio analysis on design and modelling a 22nm NMOS device with gate structure of high-k metal gate (TiO2/ TiSix) and bilayer graphene

Abd Gani, Azizul Haqeem (2020) Current ratio analysis on design and modelling a 22nm NMOS device with gate structure of high-k metal gate (TiO2/ TiSix) and bilayer graphene. Project Report. Universiti Teknikal Malaysia Melaka, Melaka, Malaysia. (Submitted)

Text (Full Text) Current ratio analysis on design and modelling a 22nm NMOS device with gate structure of high-k metal gate (TiO2 TiSix) and bilayer graphene.pdf - Submitted Version Download (928kB)

Abstract

This project is based on virtual fabrication and program code development of a 22nm NMOS device design with high-k, metal gate structure and graphene by using Silvaco software. High-k material which is Titanium Dioxide (TiO2) is used to replace Silicon Dioxide (SiO2). Polysilicon is also replaced with metal gate which is Titanium Silicide (TiSix). Additional of bi-layer graphene is added to complete the gate structure. This experiment reveals the general replication structure of the ATHENA and electrical characteristic analysis using ATLAS module. Such two simulators are paired with the Taguchi system to refine the threshold voltage (VTH) and current leakage (IOFF) electrical characteristics. The results of the device electrical characteristics after simulation obtained with VTH = 0.279852V, meanwhile for IOFF = 129.099 nA/μm which is near to prediction ITRS 2012 value which is 0.289 ± 12.7%. However, the optimization process by using Taguchi method is slightly incorrect for adjustment factor and dominant factor for VTH optimization due to incompatible combination between high-k dielectrics with TiSix metal gate contribute to the unsuccessful in completing Taguchi method. In conclusion, current ratio for the circuit is 15751.48.

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