FPGA Implementation Of Convolutional Neural Network Using SDSOC

Cheong, Jia Mun (2019) FPGA Implementation Of Convolutional Neural Network Using SDSOC. Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

Nowadays, Convolutional Neural Network is widely used on various application areas such as computer vision, speech recognition, and natural language processing. Due to massive computation of CNN, the hardware acceleration is needed to speed up the computation structure of CNN. In order to conduct hardware acceleration, hardware implementation process is needed to be done. However, the hardware implementation of Convolutional Neural Network is time consuming and requires hardware digital knowledge for writing the hardware description language to creating register-transfer level abstractions design. By using SDSoC development environment, the C programming language coding can transform to register transfer level without using hardware description language. In this project, Convolutional Neural Network architecture LeNet-5 is accelerated by applying three types of the optimization technique on SDSoC development environment. The three types of optimization technique that are applied on this project which are Loop Pipelining, Loop Unrolling and Array Partitioning. The LeNet-5 by using all the three types of the optimization techniques is achieved 3.71 times speed up compared with software implementation on the ARM Cortex A9.

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