Optimization Of 16nm DG Finfet For Reduced Variability And Enhanced Performance

Ismail, Nur Habibah (2018) Optimization Of 16nm DG Finfet For Reduced Variability And Enhanced Performance. Project Report. UTeM, Melaka. (Submitted)

Text Optimization Of 16nm DG Finfet For Reduced Variability And Enhanced Performance - Nur Habibah Ismail - 24 Pages.pdf - Submitted Version Download (1MB)

Abstract

The ev olution of electronic technology is directly proportional with the evolution of the semiconductor industry. According to Gordon Moore, he predicted that the number of transistors in integrated circuit would double every two years. Therefore, this observation can be proved by shrinking the transistor size to obtain high drive current due to the denser transistor per chip. However, the continuous miniaturization process leads to some drawbacks when it enters the nanometer scale. As this research worked on l 6nm size in gate length, there were a few approaches to solve the short channel effect (SCE) . Throughout the project, the process simulation of the transistor was performed by using a ATHENA module in Silvaco TCAD . Meanwhile, the electrical characterization of the device was implemented by using ATLAS module. In this research , the transistor was designed by employing double gate (DG) FinFET structure. Then, it was tested with three different materials such as Titanium Oxide (Ti02), Hafnium Oxide (Hf02) and Silicon Nitride (Si 3N4) as gate dielectric. From the analysis, the Titanium Oxide produced the best results for threshold voltage (Vrn), drive current (loN), leakage current (loFF) and sub-threshold swing (SS). Then, the transistor was optimized by statistical method, 2k-factorial to get the optimum response. The effect of process parameter v ariation was reduced by this technique. After optimization process, the values of V rn, loN , lo FF and SS is 0.241 V, 1589.3μA/μm , 15.82pA/μm and 97.43mV/dec respectively. All the final results are well within the International Technology Roadmap Semiconductor (ITRS) 2013 for high performance (HP) Multi Gate (MG) technology for the year 2015 . Therefore , the optimization of 16nm DG FinFET with different material dielectric using 2k-factorial was successfully achieved.

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