Design And Optimization Of A Bilayer Graphene On 22 nm PMOS Device

Raja Shahrul Nizam, Raja Fatin Hazirah (2018) Design And Optimization Of A Bilayer Graphene On 22 nm PMOS Device. Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

A bilayer grapheme on 22 nm PMOS device was optimized and analyzed to obtain the optimum value of performance parameters. The device consists of Titanium dioxide (TiO2) as a high permittivity (high-k) and Tungsten silicide (WSix) as a metal gate. The ATHENA and ATLAS modules from the Silvaco software were utilized to simulate the virtual device fabrication process and to verify the electrical properties of the device respectively. Taguchi L9 orthogonal array method was then employed to improve the device process parameters for the optimum threshold voltage (VTH) and lowest leakage current (ILEAK) in-line with International Technology Roadmap for Semiconductor (ITRS) specification which are -0.289 V ± 12.7% (VTH) and 100 nA/μm (ILEAK).The result from the signal-to noise ratio (SNR) of nominal-the-better (NTB) for VTH and smaller-the-better (STB) for ILEAK are then analysed by the percentage that affects the process parameters. The results in the simulation shows that halo tilting angle and S/D implantation are the most dominant factor and adjustment factor in affecting the VTH and ILEAK respectively. The optimized results show an outstanding device performance with VTH of -0.2893V which is 0.0261% closer to the ITRS 2012 target and ILEAK is 0.0389 nA/μm which is far lower than the prediction.

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