Design And Optimization Of 22 nm NMOS Device High-K/Metal Gate With Bi-Layer Of Graphene

Rosli, Suhail Firas (2018) Design And Optimization Of 22 nm NMOS Device High-K/Metal Gate With Bi-Layer Of Graphene. Project Report. UTeM, Melaka, Malaysia. (Submitted)

Text (24 Pages) Design And Optimization Of 22 nm NMOS Device High-K Metal Gate With Bi-Layer Of Graphene.pdf - Submitted Version Download (350kB)

Abstract

This project is based on simulation and program development of NMOS device performance by adding a bi-layer of graphene by using Silvaco software. This project exhibits general structure of the simulation for the 22 nm NMOS device after simulated by ATHENA and ATLAS module. ATHENA is the Silvaco process simulator used for device fabrication tool while ATLAS simulation module performs the device simulator procedures for electrical characteristics. These two simulator are combined with Taguchi Method in order to optimize the process parameter. Silicon Dioxide is replaced with high-k material which is Titanium Dioxide and replaced polysilicon with metal gate which is tungsten silicide. As transistor is reduce in size, the thickness also decreased to increase the gate capacitance. As the thickness of high-k metal gate material scale to 22 nm, the leakage current will increase drastically due to channel tunneling which lead to high power consumption and lower device reliability. Therefore, replacing the traditional gate material with high-k metal gate allows gate capacitance to increase without any correlation with leakage effects.

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