Design And Optimization Of 22nm PMOS Device With A Bi-Layer Oxide

Ruba'ie, Nurul Ashila (2018) Design And Optimization Of 22nm PMOS Device With A Bi-Layer Oxide. Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

Moore’s prediction about his law has created a major roadblock for the metal-oxide-semiconductor-field-effect-transistor (MOSFET) to have high performance. Therefore, a comprehensive study of 22 nm PMOS device with a bi-layer oxide has been presented in this project. The objectives are to design and simulate a bi-layer oxide on high-k / metal gate on 22 nm PMOS device by using Silvaco software and to analyse and optimize the electrical characteristics of device by using Taguchi L9 orthogonal array method. A 22 nm PMOS device with a bi-layer oxide was designed using a Silvaco software in ATHENA module while the electrical characteristics are determined by ATLAS overlay. The results of threshold voltage (Vth) and leakage current (Ioff) are -0.289 V ± 12.7% and 100 nA/μm respectively must be well within the International Technology Roadmap Semiconductor (ITRS) 2012 value. Taguchi’s Signal-to-Noise-Ratio (SNR) of nominal-the-best (NTB), the source/drain (S/D) implantation dose has been identified to be a dominant factor while compensation implant is an adjustable parameter for the device for Vth. While, by using the SNR of smaller-the-better (STB) determined the best process parameters combination for Ioff.

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