Analyse The Performance Of SOI MOSFET Device With Different Gate Spacer Materials

Manin, Aida Maziah (2018) Analyse The Performance Of SOI MOSFET Device With Different Gate Spacer Materials. Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

Along with the Industrial Revolution 4.0, there has been a great demand for continual miniaturization of the Bulk-Si MOSFET device as it improves the integrated circuit (IC) in both cost per production and performance. However, scaling down MOSFET degrades the performance of the device through increasing leakage current and short channel effect (SCE). Therefore, Silicon-On-Insulator (SOI) technology has been introduced to mitigate the SCE problems. This project is executed by using Silvaco TCAD software to simulate both fabrication process and electrical characteristics for the structure of SOI MOSFET that has been designed by following the International Technology Roadmap of Semiconductor (ITRS) 2013. Furthermore, this project facilitates the improvement of performance of 19nm SOI MOSFET using high-k material as the gate spacer. Through this project, the design of 19nm SOI MOSFET with BOX layer thickness of 30nm and titanium oxide (TiO2) as the gate spacer yields the highest drive current (Ion) of 548.78μA/μm and the lowest leakage current (Ioff) of 113.475pA/μm at the threshold voltage of 0.533V compared to other high-k materials as gate spacer and Bulk-Si MOSFET device.

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