An optimization of gate leakage in scaled MOSFET on the effect of temperature during the metal gate annealing process in Gate-Last Technology

Muhamad Nur Sadiq, Sazali (2017) An optimization of gate leakage in scaled MOSFET on the effect of temperature during the metal gate annealing process in Gate-Last Technology. Project Report. UTeM, Melaka,Malaysia. (Submitted)

Text (24 Pages) An optimization of gate leakage in scaled MOSFET on the effect of temperature during the metal gate annealing process in Gate-Last Technology.pdf - Submitted Version Download (2MB)

Abstract

This research has been done to improve the performance of 22nm n-MOSFET by study the relationship between the effect of temperature during the metal gate annealing process toward an n-type MOSFET performance.The 22nm n-type MOSFET is designed by using Gate-Last Technology.Gate-last tecnology introduced the dummy gate to withstand the high temperature throughout the annealing process then replace the gate with the metal gate at the last process.The tools utilize is Technology Computer Aided Design (TCAD).In TCAD software,silvaco's deck build ATHENA and ATLAS were used to design the physical structure of bulk MOSFET hence obtaining its characteristics.The design structure will be going through a step by step fabrication process which parameter and value are stated in International Technology Roadmap for Semiconductor(ITRS).Then I-V characteristics of the device can be analyzed by using ATLAS to show the particular performance of current device created.The objective of this experiment is to design and compare the performance of 22nm n-MOSFET when the different value of temperature during the metal gate annealing process is applied.The results indicate that the difference in the value of temperature will affect the performance of the device.The optimized temperature of annealing process for this device is 750°C.

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