FPGA Implementation Of AES Algorithm

Abdul Rahman, Mej Mohd Yazi (2016) FPGA Implementation Of AES Algorithm. Project Report. UTeM, Melaka, Malaysia. (Submitted)

Text (24 Pages) FPGA Implementation Of AES Algorithm.pdf - Submitted Version Download (471kB)

Abstract

This thesis presents an FPGA implementation of Advanced Encryption Standard (AES) algorithm. AES is an encryption technique for the purpose of protecting sensitive and valuable data from being intercepted by unwanted parties. AES is widely used in government, military and banking applications. The AES algorithm can be implemented using High Level Language such as C/C++ running on general purpose processor or Hardware. However, for the real-time high speed applications, the AES algorithm must be implemented in hardware due to its high computational requirement. In this project, the AES is mapped to a parallel digital architecture to obtain highest speed implementation. The AES digital architecture is modelled using Verilog coding, simulated and its functionality verified using ISim Xilinx ISE Design Suite. The simulation results prove correct functionality of the Verilog AES Model. The AES design has been synthesized and implemented on FPGA. System Generator Hardware Co-simulation is used to verify the design in FPGA. The output results from the hardware-co simulation match the simulation results.

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