Development Of Pesona Risc Microprocessor Architecture In FPGA

Mohd Fahmir Adzran, Ramlee (2014) Development Of Pesona Risc Microprocessor Architecture In FPGA. Project Report. UTeM, Melaka, Malaysia. (Submitted)

Text (24 Pages) Development Of Pesona Risc Microprocessor Architecture In FPGA 24 Pages.pdf - Submitted Version Download (1MB)

Abstract

Pesona is the first Malaysian made 16-bit Microprocessor designed by Malaysian Institute of Microelectronic System (MIMOS). It began when Reduce Instruction Set Computer (RISC) processor was introduced; MIMOS took this as a challenge to produce its own RISC microprocessor in 1994. Since then, there was no attempt to upgrade or continue the Pesona RISC Microprocessor and lead to the idea of implementing this microprocessor in Field Programmable Gate Array (FPGA). With the technological advancement of FPGA, there created a possibility of implementing the Pesona architecture. The objective is to emulate the original Pesona RISC architecture in FPGA platform. To test and verify the architecture Xilinx Virtex-II FPGA was used. The Pesona processor architecture has been design using Verilog HDL. At the end of the project, a processor architecture that emulates the operation of the Pesona processor was developed. Since the architecture is developed using hardware description language, there are a lots of opportunity to improve the processor design.

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