Design And Analysis Of A Low Power Operational Amplifier Using Cadence

Nabilah Sk., Abd. Aziz (2014) Design And Analysis Of A Low Power Operational Amplifier Using Cadence. Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

In this paper a low power operational amplifier consisted of two stages and operates at 1.8V power supply is design by using 130nm technology. It is designed to meet a set of provided specification. Designers are able to work at low input bias current and also at low voltage due to the unique behavior of the MOS transistors in sub-threshold region. The design of two-stage operational amplifier provides a gain of 69.73dB and a 28.406MHz of gain bandwidth product for a load of 2pF capacitor. It has CMRR of 62.93dB and output slew rate of 20V/μs. The two-stage op-amp has a PSRR+ of 99.76 dB and PSRR- of 90.91dB. The presented op-amp has an Input Common Mode Range (ICMR) of 0.8V to 1.6V and power consumption of 0.389mW. This two-stage op-amp is design using the Silterra 130nm technology library. The layout has been draw and its area had been calculated. The proposed two stage op-amp consist of NMOS current mirror as bias circuit, differential amplifier as the first stage and common source amplifier as the second stage. The first stage of an op-amp contributed high gain while the second stage contributes a moderate gain.

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