Metal Gate Process Refining Using Gate First And Gate Last Technology For 22nm N-MOSFET

Nor Idayu, Che Hussin (2015) Metal Gate Process Refining Using Gate First And Gate Last Technology For 22nm N-MOSFET. Project Report. UTeM, Melaka, Malaysia. (Submitted)

Text (24 pages) Metal Gate Process Refining Using Gate First And Gate Last Technology For 22nm N-MOSFET 24 Pages.pdf - Submitted Version Download (592kB)

Abstract

This research has been done to improve the performance of 22nm n-MOSFET using two approaches which is gate-first and gate-last technology. Gate-first technology was initially developed by Sematech and the IBM-led Fishkill Alliance and found that it has flaws with their design. In gate-first technology, directly deposited gate has caused the gate damage due to the high temperature (over 1000°C) during the annealing process. To fix the flaws, gate-last technology has been proposed. Gate-last technology was introduced by Intel, implementing it in its 45nm technology. Gate-last technology overcomes the problem by depositing the dummy gate to withstand the high temperature throughout the annealing process then replace the gate with the real gate at the last process. Basically, metal gate is always pair up with high-k dielectric. Unfortunately, high-k dielectric is not defined by the simulation tools that we used. Thus, we use SiO2 (silicon dioxide) as a dielectric constant for both processes. The metal gate used for this 22nm n-MOSFET is Titanium Nitrate (TiN). NMOS transistor was simulated using fabrication tool Silvaco ATHENA and the electrical characteristic was simulated using Silvaco ATLAS. The objective of this experiment is to design and compare the performance of 22nm n-MOSFET using gate-first and gate-last process. The results indicate that the gate-last process improves the performance of 22nm n-MOSFET in comparison with gate-first process. This is due to the undamaged metal gate during the annealing process.

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