Three Bit Subtraction Circuit Via Field Programmable Gate Array (FPGA)

Nooraisyah, Arasid (2013) Three Bit Subtraction Circuit Via Field Programmable Gate Array (FPGA). Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

This project is about to design the software and hardware simulator for a Three Bit subtraction Circuit via FPGA. By design the Three bit subtraction circuit are involved in performing the subtraction for each bit by performs operation the arithmetic and logic unit, called the Arithmetic Logic Unit (ALU). All this operation is to display at seven segment using FPGA board by using Verilog language. A FPGA is a semiconductor device containing programmable logic components called "logic blocks", and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or simple mathematical functions such as additional, subtraction, multiplication, and divisions (+, -, x, ÷). In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memories. Combination of FPGA and ALU will produce the design of three bit subtraction circuit via FPGA.

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