Design Of Shallow Source / Drain Extension (SDE) Profiles In Improving Short Channel Effect (SCES) In Nanoscale Devices

Mohd Hafiz, Sulaiman (2013) Design Of Shallow Source / Drain Extension (SDE) Profiles In Improving Short Channel Effect (SCES) In Nanoscale Devices. Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

In this era globalization, the technology of world is growth fast especially in electronic revolution. The companies compete with each other to invent the new devices that can be multitasking and many applications. The engineers become smart to design the chip with small sizes. Besides, the architecture of the chip must be concern for the better performance of the electronic devices. One of the solutions is to design of shallow source/drain extension (SDE) alternative to the conventional devices so that the performance are improved. In order to increase the mobility and the speed of the electronic devices, semiconductor technology researchers face the limitations such as short channel effect in MOSFET device as it is unavoidable in scaling. The aim of this project is to improve the short channel effect in nanoscale devices. Technology Computer Aided Design (TCAD) tool from Silvaco’s International® was used to design and simulate the structure designed in this project. Silvaco’s DEVEDIT software was used to design the structure of MOSFET according to the steps, while Silvaco’s ATLAS software was used to simulate the structure to obtain the output graph. The output graph and result analysis such as graph for transfer curves (ID –VGS) and graph for subthreshold curves (log ID –VGS) were obtain to compare the scaling the junction depth between the standard International Technology Roadmap Semiconductor (ITRS) structure with shallow source/drain extension (SDE) structure. Results analyzed in this project show the design of shallower junction depth structure improved the short channel effect for devices. Finally, this conventional NMOS has lower resistance and lower power consumption.

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