Optimization Of 19 NM SOI MOSFET With High-K Material As Gate Spacer Using Statistical Method

Sahul Hameed, Syazwani Husna (2019) Optimization Of 19 NM SOI MOSFET With High-K Material As Gate Spacer Using Statistical Method. Project Report. UTeM, Melaka, Malaysia. (Submitted)

Text (24 Pages) Optimization Of 19 NM SOI MOSFET With IDGK-K Material As Gate Spacer U Sing Statistical Method.pdf - Submitted Version Download (3MB)

Abstract

As scaling down MOSFET device degrade the device performance in term of leakage current and short channel effect (SCE). To overcome the problem, the SOI MOSFET device with high-k material such as titanium dioxide (Ti02) as gate spacer bas been introduced . However, the fluctuation and variation of ion implantation process will impact the overall power dissipation and performance. Therefore, analysis of variability has become a very important tool to predict the response variation very early in the design cycle due to process parameter spreads. This project execution is based on simulation and program development of the device. Simulation of this device fabrication will be performed by using A THEN A module while for simulation of electrical characteristics will be implemented by using ATLAS module from semiconductor TCAD tools. Semiconductor TCAD tools are computer programs which allow for the creation, fabrication and simulation of semiconductor devices. These 2 modules will be combined with Taguchi method to aid in design and optimizer the process parameter. The parameters that will be considered in this project are the drive current (Ion), leakage current (loft), threshold voltage (Vth) , current state ratio (lon/loff ratio), subthresbold swing (SS), halo implant energy, halo implant dose, Source/Drain (SID) implant dose and SID implant energy. These parameters must achieve the most optimum value that accepted by Low Power (LP) technology by International Technology Roadmap for Semiconductor (ITRS).

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