Customizable Assembler Design For Dynamic Instruction Set Architecture (ISA)

Mohamad Hazari, Zinal Ibiadin (2014) Customizable Assembler Design For Dynamic Instruction Set Architecture (ISA). Project Report. UTeM, Melaka, Malaysia. (Submitted)

Text (24 Pages) Customizable Assembler Design For Dynamic Instruction Set Architecture (ISA) 24 Pages.pdf - Submitted Version Download (556kB)

Abstract

In the development of processor architecture, one of the crucial parts is the creation of a compatible assembler to the processor's instruction set architecture (ISA). Reconfigurable processor such as UTeMRISC03 requires a flexible assembler design in order to accommodate the modification being made to its ISA. The objectives of this project are to design a customizable assembler for dynamic instruction set architecture and to verify the assembler is compatible with the UTeMRISC03 processor architecture. In order to meet the objectives, a new assembler has been designed using Visual Basic (VB). The designed software is user friendly because it is able to modify according to any design requirement. The new assembler is capable in converting an assembly language program to its instruction word dictated by the processor's opcode file. The correct object file is also generated in line with the selected ISA width determined by the users. The object file is successfully loaded to the processor architecture in the FPGA platform in order to verify its compatibility. With the customizable feature achieved in this assembler design, the assembler would be beneficial as the main tool in the development of a complete package in a reconfigurable processor development in the future.

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