Subtraction And Addition Design Using Field Programmable Gate Array (FPGA)

Muhamad Qayum, Abdullah (2014) Subtraction And Addition Design Using Field Programmable Gate Array (FPGA). Project Report. UTeM, Melaka, Malaysia. (Submitted)

Text (24 pages) Subtraction And Addition Design Using Field Programmable Gate Array (FPGA) 24 Pages.pdf - Submitted Version Download (265kB)

Abstract

This project is about to design the software and hardware simulator for a eight bit subtraction and addition circuit via Field Programmable Gate Array (FPGA). The eight bit circuits are involved in performing the subtraction and addition selected for each bit by performs operation the arithmetic and logic unit, called the Arithmetic Logic Unit (ALU). All this operation is to be displayed at seven segment using FPGA board by using Verilog Language. A FPGA is a semiconductor device, containing programmable logic components called “logic blocks”, and programmable interconnects. Logic blocks can be programmed to perform the function of basic logic gates such as AND, and XOR, or more complex combinational functions such as decoders or simple mathematical functions such as addition, subtraction, multiplication and divisions (+,-,x,+). In conclusion, eight bit subtraction and addition circuit via FPGA has been successfully designed and developed.

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