Genetic Algorithm for Very Large Scale Integration (VLSI) Test Generation

Wong, Yan Chiew and Hanissah, Mohamad @ Sulaiman and Mardiana, Bidin and David, Yap Fook Weng and Syafeeza, Ahmad Radzi (2009) Genetic Algorithm for Very Large Scale Integration (VLSI) Test Generation. Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

The Very Large Scaled of Integration (VLSI) circuit fabrication process is prone to random defects, which may affect the functionality of a device and cause erroneous outputs. As manufacturers go into volume production with 90nm designs and below, the defect detection has become a challenge in the initial yield ramp. Since the defect can result in state-holding, intermittent and pattern-dependent fault effects, these models are generally more complex. Consequently, logical testing is proven cannot guarantee the detection of the defect. In this research, analogue testing to the defect based on defective current and voltage is proposed. The magnitude of abnormal increased of power supply current is mainly subjected to the specific location in the Circuit Under Test (CUT), magnitude of input voltage and its frequency. Current VLSI defect testing methods are either keep repeating the circuit simulation based on try and error technique which is tedious or consider part of the factors only for the defect. Thus, the testing results from current procedures may not be as accurate as possible and fully covered. By using Genetic Algorithm (GA), it is capable in solving these multi objective solutions. GA is stochastic searching algorithms, it makes the searching pr?cess jumps randomly from point to point, thus allowing ~scape from the local optimum, in which other conventional optimization algorithms might land, and it searches for many sub-optimum points in parallel. This research presents an evolutionary computation algorithm for defect detection. The significant difference of defective current and the magnitude of output voltage are considered based on various sizes and location of resistors, frequencies or voltage supply magnitudes using optimization of GA. Results show that the proposed method can achieve a very high testing accuracy and simulation time.

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