Study And Modelling High-K Material For Nanoscale Gate CMOS Device

Muzalifah , Mohd Said and Afifah Maheran, Abdul Hamid and Zul Atfyi Fauzan, Mohammed Napiah and Nurliyana , Abd Mutalib and Nur Fatihah, Azmi (2013) Study And Modelling High-K Material For Nanoscale Gate CMOS Device. Project Report. UTeM, Melaka, Malaysia. (Submitted)

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Abstract

In recent years, there is a lot of design on MOSFET that has been developed to fulfill the market need. However, there are critical problem occur as the MOSFET is scaled down to the nanoscale region. The critical problem means is increases of leakage current. As the size of transistor is becoming smaller over the years thus an effort to improve MOSFET, a performance yet with decreasing its size is being explored. They are more research to improve MOSFET performances such as decrease thickness of metal oxide, channel length and other. For this project, it will base on thickness of metal oxide to produce the better MOSFET so that the analysis and comparisons can be made. This project is proposed for change Silicon Dioxide to High-K Material because of its dielectric constant. Simulation tools used will be Silvaco TCAD tools (ATHENA and ATLAS) which is simulation fabrication and electrical characteristic simulation software. The electrical performances are including Threshold voltage, Sub-threshold slope, On/Off Current and Leakage Current. During the device simulation process, using Silvaco ATLAS, the electrical parameter is extracted to investigate the device characteristic. The material has many advantages and will be describe further in each chapter.

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